This invention relates to the art of multiprocessing and, more particularly, to method and apparatus for controlling gateword acquisition in a multiprocessor write-into-cache environment. More specifically yet, this invention relates to preventing a xe2x80x9choggingxe2x80x9d condition in which a given processor is unable to gain timely acquire a gateword which is controlling access to a process or data set.
In a multiprocessor system having a write-into-cache architecture, gatewords are used in a software controlled process to prevent more than one processor from executing common code or accessing shared data at the same time. A unique gateword that is assigned to a given process or data set is tested to assure that no other processor is currently executing or accessing the information a given processor is requesting. This procedure prevents a detrimental activity from occurring when a processor changes data at the same time another processor is using it, a condition commonly labeled as xe2x80x9cprocesses stepping on each otherxe2x80x9d.
An operating system for a multiprocessor environment can have several processes that are common code elements used by all processors. (Similarly, several processes may share common data sets used by all processor.) For example, a dispatcher process may be responsible for starting or re-dispatching all processes. The dispatcher code is protected by a gateword that is heavily accessed by all processors. In a xe2x80x9cwrite-into-cachexe2x80x9d cache architecture, the gateword is siphoned from one processor to another while testing for the gateword to be opened (available).
The write-into-cache architecture increases the amount of data siphoning between caches. The siphoning process incurs significant delays when the copied data must be siphoned through multiple levels of cache. Thus, in modern multiprocessing systems, not all processors are equal when it comes to data siphoning delays. The more cache mechanisms given siphoned data must pass through, the longer it will take the data to arrive at the requesting processor.
A process decision cannot be made until the data arrives and can be tested. The delays can be sufficiently excessive as to prevent a processor with the longest siphon delays in a given condition from ever acquiring the relevant gateword before another processor has overwritten (and thus closed) it. This undesirable result is commonly called xe2x80x9choggingxe2x80x9d. (Cache interface priorities play a part in access delays, but are a necessary requirement in hardware design to sequence the access commands one at a time for proper data and status updating within the details of the cache design.)
Software systems have typically relied on hardware to mediate the gateword access controls using a read-alter-rewrite method of access. Specific gate handling instructions used this mechanism which was satisfactory when processors in a multiprocessor system had substantially the same access times within the context of processor clock speeds. As hardware designs became more complex and processor speeds increased, it also became more difficult to attain the interface speeds necessary to handle the gateword access priority without a system performance penalty. The responsibility for access to heavily used gatewords has gradually become more dependent on software mechanisms as software designers become increasingly aware of the problems that occur as a result of the hogging effect.
Most software techniques employed to handle the hogging problem are of fixed delay types that will always delay access to a gateword whether a delay is required or not. Fixed delay techniques significantly reduce system performance. This type of software technique must be tuned to the system architecture and may even have to be tuned to various gates within the operating system. Accordingly, it would be highly desirable to provide hardware assistance, in the form of additional instructions, to assist in effecting software handling of gateword control in a complex multiple processor system with a write-into-cache architecture. The present invention achieves this objective in a relatively simple and highly effective manner.
This and other objects of the invention are achieved by providing, in a multiprocessor data processing system including a memory; at least first and second shared caches; a system bus coupling the memory and the first and second shared caches; at least first, second, third and fourth processors having, respectively, first, second, third and fourth private caches with the first and second private caches being coupled to the first shared cache, and the third and fourth private caches being coupled to the second shared cache; preventing hogging of ownership of a gate control word by providing a gate control flag in each of the processors; and establishing priority for another processor to next acquire ownership of the gate control word by: broadcasting from the another processor a xe2x80x9cset gate control flagxe2x80x9d command to all processors such that setting the gate control flags establishes delays during which ownership of the gate control word will not be requested by a processor for predetermined periods established in each processor; and establishing in the another processor a shorter predetermined period than established in all other processors such that the another processor will acquire ownership of the gate control word when the one processor relinquishes ownership. Optionally, the another processor broadcasts a xe2x80x9creset gate control flagxe2x80x9d command to all processors when it has acquired ownership of the gate control word.